1. Field of the Invention
The present disclosure generally relates to the field of fabricating integrated circuits, and, more particularly, to forming electronic fuses in the metallization system of the semiconductor device for providing device-internal programming capabilities in complex integrated circuits.
2. Description of the Related Art
In modern integrated circuits, a very high number of individual circuit elements, such as field effect transistors in the form of CMOS, NMOS, PMOS elements, resistors, capacitors and the like are formed on a single chip area. Typically, feature sizes of these circuit elements are decreased with the introduction of every new circuit generation, to provide currently available integrated circuits with high performance in terms of speed and/or power consumption. A reduction in size of transistors is an important aspect in steadily improving device performance of complex integrated circuits, such as CPUs. The reduction in size of the transistors is commonly associated with an increased switching speed, thereby enhancing signal-processing performance. In addition to the large number of transistor elements, a plurality of passive circuit elements, such as capacitors, resistors and the like, are typically formed in integrated circuits that are used for a plurality of purposes.
Due to the reduced dimensions of circuit elements, not only the performance of the individual transistor elements may be increased, but also their packing density may be improved, thereby providing the potential for incorporating increased functionality into a given chip area. For this reason, highly complex circuits have been developed, which may include different types of circuits, such as analog circuits, digital circuits and the like, thereby providing entire systems on a single chip (SoC).
In modern integrated circuits, minimal features sizes have now reached approximately 50 nm and less, thereby providing the possibility of incorporating various functional circuit portions in a given chip area, wherein, however, the various circuit portions may have a significantly different performance, for instance with respect to lifetime, reliability and the like. For example, the operating speed of a digital circuit portion, such as a CPU core and the like, may depend on the configuration of the individual transistor elements and also on the characteristics of the metallization system, which may include a plurality of stacked metallization layers so as to comply with the required complex circuit layout. Thus, highly sophisticated manufacturing techniques may be required in order to provide the minimum critical feature sizes of the speed-critical circuit components. For example, sophisticated digital circuitry may be used on the basis of field effect transistors, which represent circuit components in which the conductivity of a channel region is controlled on the basis of a gate electrode that is separated from the channel region by a thin dielectric material. Performance of the individual field effect transistors is determined by, among other things, the capability of the transistors to switch from a high impedance state into a low impedance state at high speeds, wherein also a sufficiently high current may be driven in the low impedance state. This drive current capability is determined by, among other things, the length of the conductive channel that forms in the channel region upon application of an appropriate control voltage to the gate electrode. For this reason, and in view of the increasing overall packing density of sophisticated semiconductor devices, the channel length, and thus the length of the gate electrode, is being continuously reduced, which, in turn, may require an appropriate adaptation of the capacitive coupling of the gate electrode to the channel region. Consequently, the thickness of the gate dielectric material may also have to be reduced in order to maintain controllability of the conductive channel at a desired high level. However, the shrinkage of the gate dielectric thickness may be associated with an exponential increase of the leakage currents, which may directly tunnel through the thin gate dielectric material, thereby contributing to enhanced power consumption, and thus waste heat, which may contribute to sophisticated conditions during operation of the semiconductor device. Moreover, charge carriers may be injected into the gate dielectric material and may also contribute to a significant degradation of transistor characteristics, such as threshold voltage of the transistors, thereby also contributing to variability of the transistor characteristics over the lifetime of the product. Consequently, reliability and performance of certain sophisticated circuit portions may be determined by material characteristics and process techniques for forming highly sophisticated circuit elements, while other circuit portions may include less critical devices, which may thus provide a different behavior over the lifetime compared to critical circuit portions. Therefore, the combination of the various circuit portions in a single semiconductor device may result in a significant different behavior with respect to performance and reliability, wherein also the variations of the overall manufacturing process flow may contribute to a further discrepancy between the various circuit portions. For these reasons, in complex integrated circuits, frequently, additional mechanisms may be implemented so as to allow the circuit to be adapted in view of performance of certain circuit portions to comply with the performance of other circuit portions, for instance after completing the manufacturing process and/or during use of the semiconductor device, for instance when certain critical circuit portions may no longer comply with corresponding performance criteria, thereby requiring an adaptation of certain circuit portions, such as readjusting an internal voltage supply, re-adjusting the overall circuit speed and the like.
For this purpose, so-called electronic fuses or e-fuses may be provided in the semiconductor devices, which may represent electronic switches that may be activated once in order to provide a desired circuit adaptation. Hence, the electronic fuses may be considered as having a high impedance state, which may typically also represent a “programmed” state, and having a low impedance state, typically representing a non-programmed state of the electronic fuse. Since these electronic fuses have a significant influence on the overall behavior of the entire integrated circuit, a reliable detection of the non-programmed and the programmed state has to be guaranteed. Furthermore, since typically these electronic fuses may be actuated only once over the lifetime of the semiconductor device under consideration, a corresponding programming activity has to ensure that a desired programmed state of the electronic fuse is reliably generated in order to provide well-defined conditions for the further operational lifetime of the device. With the continuous shrinkage of critical device dimensions in sophisticated semiconductor devices, however, the reliability of the programming of corresponding electronic fuses may require tightly set margins for the corresponding voltages and currents used to program the electronic fuses, which may not be compatible with the overall specifications of the semiconductor devices, or may at least have a severe influence on the flexibility of operating the device.
In conventional strategies, the fuses are formed on the basis of a semiconductor material, such as polysilicon and the like, as may typically also be used for forming conductive lines in the device level of the semiconductor device, for instance for gate electrode structures of field effect transistors, wherein the per se negative effect of electromigration in combination with a charge carrier depletion in the semiconductor material may be taken advantage of in order to initiate a significant deterioration of the electronic fuse by applying a current for programming the fuse into a high impedance state. As is well known, electromigration is a phenomenon in which a high current density in DC operated conductive lines may result in a “diffusion” of metal atoms caused by the momentum transfer of the high-density electron flow. In polysilicon lines, typically, a metal silicide material is provided to enhance the conductivity of the semiconductor-based material, and a pronounced electromigration effect may, thus, be intentionally initiated in the metal silicide material, thereby increasingly contributing to a metal depletion at the cathode, while a material agglomeration is observed towards the anode. Furthermore, the electromigration effect may be further increased by locally creating elevated temperatures, which may be accomplished by locally providing a desired high resistance for a given total current that is to be driven through the electronic fuse. Consequently, appropriate lateral dimensions for fuse bodies, i.e., the portions of the electronic fuses in which an electromigration effect and, thus, the line degradation is to be initiated, are provided for a given material composition and thickness of the electronic fuses, in accordance with the overall process strategy for forming the sophisticated gate electrode structures of the field effect transistors. For example, the cross-sectional area of the fuse bodies may be reduced by selecting a minimum width of the fuse bodies, while, at the same time, the length of the fuse bodies may be increased, thereby increasing the overall electromigration effect.
Due to the increasing overall complexity of semiconductor devices, however, an increased number of electronic fuses has to be provided, which, however, may result in a significant consumption of valuable chip area in the device level of the semiconductor devices. Furthermore, recently, very complex gate electrode structures are being implemented in sophisticated semiconductor devices in order to enhance transistor performance, wherein the conventional gate materials, such as silicon dioxide as a gate dielectric and polysilicon in combination with a metal silicide as an electrode material, are replaced by a high-k dielectric material in combination with an electrode metal, such as aluminum and the like. As a consequence, materials of improved conductivity may be implemented in the fuse bodies, unless additional significant efforts have to be made so as to locally provide the conventional polysilicon/metal silicide material system for the electronic fuses. Thus, the incorporation of highly conductive metals, such as aluminum and the like, in the device level and the demand for further increasing the overall packing density in semiconductor devices have recently resulted in the concept of providing electrically programmable fuses on the basis of metals, thereby also considering the possibility of implementing “three-dimensional” fuses, which may, thus, be provided in the metallization system of the semiconductor device.
In complex semiconductor devices, typically, metallization systems, i.e., a plurality of stacked metallization levels, are provided, in which metal lines provide the inner level electrical connection, while so-called vias, i.e., “vertical” interconnect structures, may provide the intra-level connection, thereby providing the complex interconnect network in order to electrically connect the individual circuit elements provided in the device level according to the required circuit layout. The metal lines and vias typically comprise a highly conductive metal, such as copper, which may exhibit a reduced electromigration effect and an overall higher conductivity compared to aluminum. Due to copper's characteristic to readily diffuse in a plurality of well-established dielectric materials, such as silicon dioxide and silicon dioxide-based low-k dielectric materials, which are typically used in combination with copper material in order to reduce signal propagation delay caused by the parasitic capacitance in the metallization system, a conductive barrier material, such as tantalum, tantalum nitride and the like, is to be formed in the metal lines and vias.
Since reliability and lifetime of complex semiconductor devices may essentially be determined by the duration of the metallization system, significant efforts are being made in investigating line degradation mechanisms in metallization systems caused by electromigration, since a complex interaction between dielectric materials, the conductive copper material and the geometry of conductive parts has to be taken into consideration in order to quantitatively estimate the overall performance and degradation of metal features over a lifetime. On the other hand, any technical knowledge about the electromigration mechanisms in copper-based metallization systems may be advantageously used in designing appropriate electronic fuses in which the electromigration effect is exploited for obtaining a permanent line degradation, which thus may reliably indicate a programmed state of the electronic fuse.
With reference to FIGS. 1a-1b, a metal fuse formed in a metallization system may be described in more detail in order to describe some of the disadvantages associated with conventional metal fuses.
FIG. 1a schematically illustrates a top view of a semiconductor device 100 comprising a metallization system 150, which is formed on the basis of copper material in combination with sophisticated dielectric materials, such as low-k dielectric materials and the like. The metallization system 150 may typically comprise a plurality of stacked metallization layers, wherein, for convenience, a first metallization layer 110 is schematically illustrated so as to include first and second metal lines 111, 112. The metal lines 111, 112 are typically embedded in a dielectric material that is not shown in FIG. 1a and which is described with reference to FIG. 1b. Moreover, a second metallization layer 120 is provided which comprises an electronic fuse 130, which may be represented by a metal line 131 in combination with a plurality of vias 133, 134A, 134B which connect the metal line 131 with the metal lines 112, 111, respectively. In the example shown in FIG. 1a, the electronic fuse 130 is designed so as to be operated on the basis of a DC current pulse in which an electron flow may be directed from the metal line 112 through the via 133 into the metal line 131 and further into the vias 134A, 134B into the metal line 111. According to this configuration, the electronic fuse 130 is designed such that, upon establishing an appropriate current density in the electronic fuse 130, line degradation may occur in a well-defined portion of the electronic fuse 130, which, in the example shown, is represented by the via 133 and a portion of the metal line 131 formed between the via 133 and the via 134A and having a length indicated by 130L. Similarly, a width 130W of the metal line 131 may be selected in accordance with the design rules for the metallization layer 120, that is, typically, the width 130W is selected so as to correspond to the minimum critical dimension in the metallization layer 120 in order to provide a reduced cross-sectional area in the metal line 131, thereby enhancing the generation of heat in the metal line 131 and thus also enhancing electromigration in the electronic fuse 130. Similarly, the length 130L may be appropriately adapted in view of the width 130W and a thickness of the metal line 131 in order to obtain the desired electronic characteristics of the electronic fuse 130.
FIG. 1b schematically illustrates a cross-sectional view of the semiconductor device 100 according to the line Ib. As illustrated, the device 100 comprises a substrate 101, which is to be understood as any appropriate carrier material and an appropriate semiconductor material, in and above which circuit elements, such as transistors and the like, are provided, which, for convenience, are not shown in FIGS. 1a-1b. It should be appreciated that respective circuit elements may include sophisticated transistors, such as field effect transistors having a gate length of 50 nm and less in sophisticated devices. Moreover, corresponding circuit elements may also include any support circuitry for the electronic fuse 130 in order to establish a desired current flow therein upon programming the fuse 130 and also to determine the status of the electronic fuse 130. For example, corresponding transistors for supplying the programming current may be provided with an appropriate transistor width in order to reliably switch on and off current required for programming the electronic fuse 130 so that the transistor size has to be adapted to the electronic characteristics of the fuse 130. Furthermore, the semiconductor device 100 comprises any appropriate contact structure (not shown) so as to provide an interface between semiconductor-based circuit elements and the metallization system 150. The metallization layer 110 comprises an appropriate dielectric material 115, which may, at least partially, be provided in the form of a low-k dielectric material, depending on the electronic performance required in the metallization layer 110. As illustrated, the metal lines 111, 112 are embedded in the dielectric material 115 and may typically comprise a conductive bulk or core metal 112A in the form of copper and a conductive barrier material or material system 112B, such as tantalum nitride, tantalum and the like. Furthermore, an etch stop material or a dielectric barrier layer 116, for instance in the form of silicon nitride, nitrogen-enriched silicon carbide and the like, is formed on the dielectric material 115 and on the metal lines 111, 112.
Similarly, the metallization layer 120 comprises a dielectric material 125, such as a low-k dielectric material and the like, in which the electronic fuse 130, i.e., the metal line 131 and the vias 133, 134A, 134B, are embedded. Also in this case, a highly conductive copper core metal 131A in combination with an appropriate barrier material 131B is provided. Additionally, a dielectric etch stop material or cap layer 126, which may have basically the same configuration as the layer 116, is formed on the dielectric material 125 and the metal line 131.
The semiconductor device 100 as illustrated in FIGS. 1a-1b may be formed on the basis of the following process strategies. After forming any semiconductor-based circuit elements in and above the substrate 101, a contact structure is provided, for instance on the basis of well-established manufacturing strategies. Thereafter, the metallization system 150 may be formed, for instance by depositing the dielectric material 115 for the metallization layer 110 on the basis of any appropriate deposition technique. It should be appreciated that one or more metallization layers may be formed below the metallization layer 110 if considered appropriate. Thereafter, the dielectric material 115 is patterned so as to form appropriate trenches for the metal lines 111, 112, which are subsequently filled with the barrier material 112B and the copper material 112A. After the removal of any excess material, the etch stop layer 116 is provided on the basis of any appropriate deposition technique, wherein, if required, a conductive cap material (not shown) may be formed on the copper material 112A. Similarly, the metallization layer 120 is formed by depositing the dielectric material 125 and patterning the same so as to provide openings for the vias 133, 134A, 134B and a trench for the metal line 131A. It should be appreciated that openings for other metal lines and vias are to be concurrently formed in the metallization layer 120, which may be accomplished on the basis of given design rules, which determine the minimum line width and spaces that may be reliably formed in the metallization layer 120 for given process-related variations. As discussed above, the geometry of the electronic fuse 130 has to be adapted in view of achieving the desired line degradation of the electronic fuse 130 for given design rules for the metallization layer 120. That is, a thickness 130T and the width 130W (FIG. 1a) may be substantially determined by the overall design rules since, for instance, the width 130W cannot be reduced beyond the minimum critical feature size in the metallization layer 120 without introducing significant non-uniformities. Consequently, the length 130L (FIG. 1a) is appropriately selected, typically as a compromise between space consumption and acceptable overall conductivity of the fuse 130, in order to provide the required electronic characteristics. That is, selecting an increased length may generally result in a higher resistivity of the electronic fuse 130 which, on the other hand, may consume more space in the metallization system 150. On the other hand, a reduced length may require significantly increased programming current pulses, which in turn may thus require correspondingly dimensioned transistors in the device level of the device 100, which may thus also contribute to an increased lateral size of the semiconductor device 100. Typically, electronic fuses formed in the metallization system 150 may nevertheless require a programming current of a magnitude that is up to three times and higher compared to conventional semiconductor-based electronic fuses provided in the device level, as discussed above.
Upon operating the device 100, a current flow 102 is established in a flow path when programming the electronic fuse 130, wherein a portion of the current flow path is represented by the metal line 112, the via 133, the metal line 131, the vias 134A, 134B and the metal line 111. As indicated, the electron flow is directed from the metal line 112 to the metal line 111 via the electronic fuse 130. As previously indicated, electromigration is a highly complex dynamic process in which the momentum exchange between charge carriers, that is electrons, and metal atoms, i.e., copper atoms, may result in a collective migration of the metal atoms when a sufficiently high current density is achieved. Since, generally, reduced cross-sectional areas are provided in the metal lines of sophisticated metallization systems, and due to the fact that, in principle, the metal lines are confined in a dielectric material allowing an efficient heat transfer into the surrounding chip area, extremely high current densities of approximately 106 ampere per m2 may be achieved, thereby resulting in significant electromigration effects. Thus, unless the metallization structure of a semiconductor device is designed and manufactured in such a way that such high current densities may be reliably avoided in any metal region of the semiconductor device, electromigration will occur during the operation of the device 100. Thus, great efforts are being made in appropriately estimating the electromigration effect in metallization systems and thus estimating the lifetime of the metallization system, since manufacturing substantially “immortal” metallization structures would require significantly increased overall dimensions, which is not compatible with economic constraints in view of producing sophisticated semiconductor devices. On the other hand, in the electronic fuse 130, the electromigration effect may be intentionally induced in order to obtain a high ohmic state as the programmed status of the electronic fuse 130. To this end, the via 133 and the metal line 131 may be provided with a configuration so as to intentionally create significant damage and thus line degradation upon establishing a current flow in the electronic fuse 130. Thus, electromigration may occur in the via 133 and the metal line 131 so that, increasingly, metal may be transported along the current flow direction, thereby densifying the material in the metal line towards the anode of the electronic fuse 130, i.e., towards the vias 134A, 134B. On the other hand, a material depletion may occur within the via 133 and the metal line 131 in an area in the vicinity of the via 133. It should be appreciated that significant electromigration effects in the metal line 112 may be avoided by selecting appropriate cross-sectional dimensions and thus providing a reduced current density, while additionally the barrier material 131B at the bottom of the via 133 may also suppress any copper diffusion from the metal line 112 into the via 133. Similarly, significant electromigration may be avoided within the vias 134A, 134B due to the overall increased cross-sectional area. Consequently, the material accumulation towards the vias 134A, 134B and the material depletion in the vicinity of the via 133 may thus result in a significant modification of the conductivity state of the electronic fuse 130, which may be detected by any appropriate peripheral circuitry.
As indicated above, despite an efficient electromigration effect, nevertheless, significantly higher currents may be required for reliably programming the metal fuse 130. Due to the overall increased conductivity of metal-based fuses compared to semiconductor-based fuses, the generation of any heat, which may also increase the overall electromigration effect upon programming the fuse 130, may be reduced, thereby also contributing to increased total current values upon “blowing” the electronic fuse 130. Furthermore, the desired electromigration and thus material migration along the metal line 131 towards the vias 134A, 134B may finally result in copper extrusion, i.e., in the migration of copper from the metal line 131 into the surrounding dielectric material 125, which may be less desirable, in particular when using sophisticated low-k dielectric materials, since then significant copper diffusion may occur in the material 125 in a highly non-predictable manner. In order to suppress non-predictable copper extrusion into the dielectric material 125, frequently, additional “extrusion” lines are provided, i.e., metal lines adjacent to the metal line 131, thereby appropriately “confining” the copper extrusion to a specific area within the dielectric material 125. In this case, however, the thermal conditions may be significantly affected by the presence of additional extrusion lines, since these metal lines may act as efficient heat sinks for dissipating any waste heat generated in the electronic fuse 130, thereby requiring even further increased current values upon reliably programming the electronic fuse 130.
The present disclosure is directed to various devices that may avoid, or at least reduce, the effects of one or more of the problems identified above.